1. Field of the Invention
The present invention generally relates to computer memory systems, and in particular to an architecture and circuitry for memory chips using burst mode memory access.
2. Description of Related Art
Computer memory systems utilize various techniques for enhancing performance of the memory system. One such technique is "burst mode" memory access. A typical burst mode access begins when a memory controller applies an initial address within a burst address space to a memory chip in the memory system, and instructs the memory chip to load the address. After a specific, predetermined amount of time (usually 2 clock cycles), the memory chip responds with the data stored at the initial address. At the next clock cycle, the memory chip outputs data from a next address within the burst address space of the initial address. Typically, the addresses within the burst address space are accessed sequentially. For example, if the initial address applied to the memory chip is address 0, then after two clock cycles, the data from address 0 is available from the memory chip. Then, on the next single clock cycle, the memory chip delivers data from address 1, and on the next single clock cycle, the memory chip delivers data from address 2, and so on. Improved memory system performance is achieved since data is available on every clock cycle, after the initial address is presented to the memory chips.
Burst mode sequences are typically either "linear sequential" (e.g., AMD, and Motorola burst sequences) or "aligned sequential" (e.g., Intel burst sequences), and may have a burst address space of any size, although four-word and 256-word burst address space sizes are typical. For memory chips to be used for burst mode access, burst mode processing circuitry is provided directly on the memory chip. More specifically, a means is provided directly on the chip for loading the initial address, generating sequential addresses within the burst address spaces, and accessing the data at the initial and sequentially-generated addresses, based on a predefined burst mode sequence and burst addressing space size.
Thus, a typical prior art burst mode memory chip receives an initial address and internally advances the initial address according to a predefined burst mode address sequence and burst address space size. The chip then applies the burst address to a memory array to access data at each burst address location. Such prior art chips only access one location in memory array at a time and the delay in accessing the sequential data can be substantial. Furthermore, such chips are typically not user programmable. In other words, the burst mode sequence and the burst mode address size are not selectable. Rather each memory chip is uniquely designed to support only one burst mode sequence and only one burst address space size.
One example of a burst mode addressing system is an aligned sequential burst mode provided by Intel, hereinafter also referred to as the "Intel Burst Mode". In Intel Burst Mode, unlike sequential burst modes, addresses are not accessed in sequence, rather higher-ordered addresses are typically accessed before corresponding lower-ordered addresses. For example, for a burst space of four words, accessing may occur in the sequence of 1,0,3,2 or 3,2,1,0, with higher ordered addresses 1 and 3 being accessed before corresponding lower-ordered addresses 0 and 2, respectively. A problem occurs in generating the aligned sequential sequence of addresses based on an initially received address. To generate the sequence of addresses for an aligned sequential mode, an initially received address is typically exclusively ORed with the output of a binary up-counter which is always initialized to zero. Table I illustrates an example of the exclusive OR operation wherein the initial address is binary 11.
TABLE I ______________________________________ External Internal Address Counter Address ______________________________________ Initial 11 .sym. 00 = 11 3 Address 1st Burst 11 .sym. 01 = 10 2 2nd Burst 11 .sym. 10 = 01 1 3rd Burst 11 .sym. 11 = 00 0 ______________________________________
As can be seen from Table I, an aligned sequential address sequence is achieved using the exclusive OR operation. However, to achieve the exclusive OR operation, a pair of exclusive OR logic gates are used within the memory system, resulting in at least one and one-half gate delays, often more.
A second general technique for enhancing memory chip performance is to provide interleaved memory arrays. A conventional interleaved memory provides an "even" memory bank and an "odd" memory bank. Data having even memory addresses are stored in the even memory bank. Data having odd memory addresses are stored in the odd memory bank. Hence, any two sequential memory locations are stored in separate memory banks. If the two sequential memory addresses are to be accessed, a first memory location is read from the first memory bank and, while the first memory bank is read, the second memory bank is pre-charged. Then, the second memory location is read from the second memory bank, while the first memory bank is pre-charged. Hence, if two sequential memory locations are accessed, the data stored at the locations may be fetched quickly without any intervening pre-charge cycles required for typical random access memory.
However, conventional interleaved memory systems do not necessarily provide optimal data output speed. If data addresses are not received and processed sequentially, then the advantages of providing interleaved memories is largely lost. As an example, some systems provide only for a statistical or probabilistic enhancement and processing time. One such exemplary system stores all data corresponding to even pages of memory in an even memory bank and all data corresponding to odd pages of memory in an odd memory bank. Two pages of memory are read in an interleaved manner by alternatingly accessing addresses from the even page memory bank and from the odd page memory bank. A first address occurring within the even page is received. If a subsequent address is received that is not in the next odd page, then the page containing the received address must be precharged. Thus, the advantages of the interleaving are greatly reduced because the system provides interleaved access only to addresses that occur within sequential pages.
It would be desirable to achieve the advantages of both burst mode memory access and interleaved memory access in a single memory chip, particularly for electrically programmable read-only memory (EPROM) chips, as well as for other memory devices such as flash erasable EPROMs (EEPROMs) or static random access memory (SRAM) chips. It would also be desirable to provide for aligned sequential burst access without the aforementioned gate delays inherent in prior art aligned sequential memory systems. It would also be desirable to provide a means to adjust or select the burst address space size and burst address sequencing mode.